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INTEGRATED CIRCUITS
DATA SHEET
UDA1320ATS Low-cost stereo filter DAC
Preliminary specification Supersedes data of 1999 Oct 11 File under Integrated Circuits, IC01 2000 Jan 10
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9 9.1 9.2 9.3 10 11 12 13 14 15 15.1 15.2 16 17 18 18.1 18.2 18.3 18.4 19 20 FEATURES General Multiple format input interface DAC digital sound processing Advanced audio configuration APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION System clock Application modes Multiple format input interface Static pin mode Pin compatibility Interpolation filter (DAC) Noise shaper Filter-Stream DAC L3 INTERFACE DESCRIPTION The L3 interface Data transfer mode Programming the features LIMITING VALUES HANDLING QUALITY SPECIFICATION THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS Analog Digital APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
UDA1320ATS
2000 Jan 10
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
1 1.1 FEATURES General
UDA1320ATS
* Low power consumption. * 2.7 to 3.6 V power supply. * Selectable control via L3 microcontroller interface or via static pin control. * 256, 384 and 512fs system clock (fsys), selectable via the L3 interface or 256 and 384fs clock mode via static pin control * supports sampling frequencies from 16kHz to 48kHz. * Integrated digital filter plus non inverting DAC Digital-to-Analog Converter (DAC). * Easy application and no analog post filtering required for DAC. * Slave mode only applications. * Small package size (SSOP16). 1.2 * Multiple format input interface
2
APPLICATIONS
* Portable digital audio equipment, see Fig.8. * Set-top boxes 3 GENERAL DESCRIPTION
The UDA1320ATS/N2 is a single-chip non inverting stereo DAC employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in digital audio equipment which incorporates playback functions. The UDA1320ATS/N2 supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB-justified serial data format with word lengths of 16, 18 and 20 bits. The UDA1320ATS/N2 can be used in two modes, either L3-mode or static pin mode. In the L3-mode, all digital sound processing features must be controlled via the L3 interface, including the selection of the system clock setting. In the two static-modes, the UDA1320ATS/N2 can be operated in the 256fs and 384fs system clock mode. The mute, de-emphasis for 44.1 kHz and 4 digital input formats (I2S and 16, 18, 20 bits LSB formats) can be selected via static pins. The L3 interface cannot be used in this application mode, also, volume control is not available in this mode.
MSB-justified and LSB-justified 16,18 and 20 bits format compatible (in L3-mode).
I2S-bus,
* I2S-bus and LSB-justified 16,18 and 20 bits format compatible in static mode. * 1fs input format data rate. 1.3 DAC digital sound processing
* Digital logarithmic volume control via L3. * Digital de-emphasis for 32, 44.1 and 48 kHz fs via L3 or 44.1 kHz fs via static pin control. * Soft mute via static pin control or via L3 interface. 1.4 Advanced audio configuration
* Stereo line output (under L3 volume control) * High linearity, wide dynamic range, low distortion.
4
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm VERSION SOT369-1
UDA1320ATS
SSOP16
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
5 QUICK REFERENCE DATA SYMBOL Supply VDDA VDDD IDDA IDDD Tamb DAC Vo(rms) (THD + N)/S S/N cs Tamb Notes 1. the output voltage has been changed with respect to the UDA1320TZ/N1. 2. the output voltage scales linearly with the power supply voltage. 6 BLOCK DIAGRAM
VDDD 4 1 2 3 VSSD 5 7 11 DIGITAL INTERFACE CONTROL INTERFACE 10 9 8
UDA1320ATS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
analog supply voltage digital supply voltage DAC supply current digital supply current ambient temperature
2.7 2.7 - - -40 note 1, 2 at 0 dB at -60 dB; A-weighted code = 0; A-weighted - - - - - -40
3.3 3.3 6.5 3.0 - 1.0 -90 -38 100 100 -
3.6 3.6 - - +85 - -85 -35 95 - +85
V V mA mA
C
output voltage (RMS value) total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio channel separation ambient temperature
V dB dB dB dB
C
handbook, full pagewidth
BCK WS DATAI
APPSEL APPL0 APPL1 APPL2 APPL3
UDA1320A
6
VOLUME/MUTE/DE-EMPHASIS
SYSCLK
INTERPOLATION FILTER
NOISE SHAPER
VO(L)
14
DAC
DAC
16
VO(R)
13 VDDA
15 VSSA
12 VREF(DAC)
MGM816
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
7 PINNING SYMBOL BCK WS DATAI VDDD VSSD SYSCLK APPSEL APPL3 APPL2 APPL1 APPL0 VREF(DAC) VDDA VO(L) VSSA VO(R) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bit clock word select data input digital power supply digital ground system clock: 256fs, 384fs, 512fs application mode select application pin 3 application pin 2 application pin 1 application pin 0 DAC reference voltage analog supply voltage left output voltage analog ground right output voltage DESCRIPTION 8 8.1
UDA1320ATS
FUNCTIONAL DESCRIPTION System clock
The UDA1320ATS/N2 operates in slave mode only. This means in all applications the system devices must provide the system clock. The system frequency is selectable and depends on the mode of operation. The options are 256fs, 384fs and 512fs for the L3 mode and 256fs plus 384fs for the static mode. The system clock must be locked in frequency to the digital interface input signals. The UDA1320ATS/N2 supports sampling frequencies from 16kHz up to 48kHz 8.2 Application modes
The application mode can be set with the tri-value APPSEL pin, to L3 mode (APPSEL = VSSD) or to either of two static modes (APPSEL = 0.5VDDD or APPSEL = VDDD). See Table 1 for APPL0 to APPL3 pin functions (active = HIGH). Table 1 Selection modes via APPSEL (note 1) APPSEL PIN VSSD 0.5VDDD (384fs) MUTE DEEM SF0 SF1 VDDD (256fs) MUTE DEEM SF0 SF1
handbook, halfpage
BCK 1 WS 2 DATAI 3 VDDD 4 VSSD 5 SYSCLK 6 APPSEL 7 APPL3 8
MGM817
16 VO(R) 15 VSSA 14 VO(L)
APPL0 APPL1 APPL2 APPL3
TEST L3CLOCK L3MODE L3DATA
UDA1320A
13 VDDA 12 VREF(DAC) 11 APPL0 10 APPL1 9 APPL2
For example, in static pin control mode, the output signal can be soft muted by setting APPL0 HIGH. De-emphasis can be switched on for 44.1 kHz by setting APPL1 HIGH. APPL1 LOW will disable de-emphasis. Note that when L3 interface is used, an L3 initialisation must be done when the IC is powered up! In L3 mode pin APPL0 must be set to LOW.
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
8.3 Multiple format input interface
UDA1320ATS
IMPORTANT: UDA1320ATS/N2 differs from the UDA1320TZ/N1 with respect to: * in the static mode 384fs is supported instead of 512fs. * the output voltage of the DAC. In the UDA1320TZ/N1 this is 800mVrms at 3.0V, now it is 1Vrms at 3.3V power supply 8.6 Interpolation filter (DAC)
L3 mode: * I2S-bus with data word length of up to 20 bits * MSB-justified format with data word length up to 20 bits * LSB-justified format with data word length of 16, 18 or 20 bits. 8.4 Static pin mode
The UDA1320ATS/N2 supports the following data input name formats in the static pin mode (via SF0 and SF1): * I2S bus with data word length of up to 20 bits * LSB-justified format with data word length of 16, 18 or 20 bits. See Table 2, for the static pin codes of the 4 formats, selectable via SF0 and SF1. The UDA1320ATS/N2 also accepts double speed data for double speed data monitoring purposes. Table 2 Input format selection using SF0 and SF1 FORMAT I2S LSB-justified 16 bits LSB-justified 18 bits LSB-justified 20 bits SF0 0 0 1 1 SF1 0 1 0 1
The digital filter interpolates from 1 to 128fs by cascading a recursive filter and a FIR filter, see Table 3. Table 3 Interpolation filter characteristics ITEM Pass-band ripple Stop band Dynamic range 8.7 Noise shaper CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.1 -50 108
The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter-Stream DAC (FSDAC). 8.8 Filter-Stream DAC
The formats are illustrated in Fig.3. Left and right data-channel words are time multiplexed. The WS signal must have 50% duty-factor for all LSB-justified modes. For BCK and WS holds that the BCK frequency must be equal or smaller then 64 times WS, or fBCK =< 64*fWS in both L3 and static mode. 8.5 Pin compatibility
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to be analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales linearly with the power supply voltage.
In L3 interface mode the UDA1320ATS/N2 can be used on boards that are designed for the UDA1322. The software for UDA1322 can be used for the UDA1320ATS/N2 to control de-emphasis, volume control and mute and also the status settings like system clock setting and input data format.
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DATAI MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB WS LEFT 18 BCK DATAI MSB B2 B3 B4 B17 LSB MSB B2 B3 B4 B17 LSB 17 16 15 2 1 18 RIGHT 17 16 15 2 1 LSB-JUSTIFIED FORMAT 18 BITS
Philips Semiconductors
handbook, full pagewidth
Low-cost stereo filter DAC
WS 1 BCK DATAI MSB 2
LEFT 3 8 1 2
RIGHT 3
8
B2
LSB MSB
B2 INPUT FORMAT I2S-BUS
LSB MSB
WS 1 BCK DATAI MSB B2 2
LEFT 3 8 1 2
RIGHT 3 8
LSB MSB
B2
LSB MSB MSB-JUSTIFIED FORMAT
B2
WS
LEFT 16 15 2 1
RIGHT 16 15 2 1
BCK
Preliminary specification
WS 20 BCK DATAI MSB B2 19
LEFT 18 17 16 15 2 1 20 19 18
RIGHT 17 16 15 2 1
UDA1320ATS
B3
B4
B5
B6
B19
LSB
MSB
B2
B3
B4
B5
B6
B19
LSB
MBK071
LSB-JUSTIFIED FORMAT 20 BITS
Fig.3 Serial interface; input format I2S-bus.
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
9 9.1 L3 INTERFACE DESCRIPTION The L3 interface
UDA1320ATS
Data transfer can only be in one direction, consisting of input to the UDA1320ATS/N2 to program sound processing and other functional features. Data bits 7 to 2 represent a 6-bit device address, bit 7 being the MSB. The address of the UDA1320ATS/N2 is 000101 (bit 7 to bit 2). If the UDA1320ATS/N2 receives a different address, it will deselect its microcontroller interface logic. 9.2 Data transfer mode
The following system and digital sound processing features can be controlled in the microcontroller mode of the UDA1320ATS/N2: * System clock frequency * Data input format * De-emphasis for 32 kHz, 44.1 kHz and 48 kHz * Volume * Soft mute. The exchange of data and control information between the microcontroller and the UDA1320ATS/N2 is accomplished through a serial hardware interface comprising the following pins: * L3DATA * L3MODE * L3CLOCK. Information transfer through the microcontroller bus is organized in accordance with the L3 format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 6). The address mode is required to select a device communicating via the L3 bus and to define the destination registers for the data transfer mode.
The selected address remains active during subsequent data transfers until the UDA1320ATS/N2 receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, see Fig.6. The maximum input clock and data rate is 64 fs. All transfers are by 8-bit bytes. Data will be stored in the UDA1320ATS/N2 after reception of a complete byte. See Fig.5 for a multi-byte transfer. Table 4 BIT 1 0 0 1 1 Selection of data transfer BIT 0 0 1 0 1 not used STATUS (system clock frequency, data input format) not used TRANSFER DATA (volume, de-emphasis, mute)
handbook, full pagewidth
L3MODE t h(L3)A t su(L3)A L3CLCK tCLK(L3)L tCLK(L3)H t su(L3)A
t h(L3)A
Tcy(CLK)(L3) t su(L3)DA t h(L3)DA
L3DATA
BIT 0
BIT 7
MBK072
Fig.4 Timing address mode.
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
handbook, full pagewidth
tstp(L3)
L3MODE
L3CLK
L3DATA
address
data byte #1
data byte #2
address
MBK074
Fig.5 Multi-byte transfer.
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLCK
th(L3)DA
tsu(L3)DA
th(L3)DA
L3DATA write
BIT 0
BIT 7
MBK073
Fig.6 Timing for data transfer mode.
The sound feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred (`STATUS' or `DATA' transfer). This is performed in the address mode using bit 1 and bit 0, see Table 4,. The settings that can be controlled with `STATUS' transfer are given in table 5, and
the settings that can be controlled using `DATA' transfer are given in table 6. The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) is the value that is placed in the selected registers.
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
Table 5 Data transfer of type `status'
UDA1320ATS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 1 Table 6 0 0 SC1 0 SC0 0 IF2 0 IF1 0 IF0 0 0 0
REGISTER SELECTED System Clock frequency (1 : 0); data Input Format (2 : 0) reserved
Data transfer of type `data' REGISTER SELECTED Volume Control (5 : 0) reserved DE-emphasis (1 : 0); MuTe default setting Volume control: a 6-bit value to program the volume attenuation (VC5 to VC0), 0 to - dB in steps of 1 dB. Table 9 VC5 0 0 0 0 : 1 1 512fs 384fs 256fs not used De-emphasis: a 2-bit value to enable the digital de-emphasis filter. Table 10 De-emphasis settings FUNCTION I2S bus LSB-justified, 16 bits LSB -justified, 18 bits LSB-justified, 20 bits MSB-justified not used not used not used MT FUNCTION no muting muting 0 1 Mute: a 1-bit value to enable the digital mute. Table 11 Mute setting DE1 0 0 1 1 DE0 0 1 0 1 FUNCTION no de-emphasis de-emphasis, 32 kHz de-emphasis, 44.1 kHz de-emphasis, 48 kHz Volume settings VC4 0 0 0 0 : 1 1 VC3 0 0 0 0 : 1 1 VC2 0 0 0 0 : 1 1 VC1 0 0 1 1 : 0 1 VC0 0 1 0 1 : 1 1 VOLUME (dB) 0 0 -1 -2 : -60 -
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 1 1 9.3 0 1 0 1 VC5 0 0 0 VC4 0 DE1 0 VC3 0 DE0 0 VC2 0 MT 0 VC1 0 0 0 VC0 0 0 1
Programming the features
When the data transfer of type `STATUS' is selected, the features SYSTEM CLOCK FREQUENCY and DATA INPUT FORMAT can be controlled. System clock frequency: a 2-bit value to select the used external clock frequency. Table 7 SC1 0 0 1 1 System clock settings SC0 0 1 0 1 FUNCTION
Data input format: a 3-bit value to select the data format. Table 8 IF2 0 0 0 0 1 1 1 1 Data input format settings IF1 0 0 1 1 0 0 1 1 IF0 0 1 0 1 0 1 0 1
When the data transfer of type `DATA' is selected, the features VOLUME, DE-EMPHASIS and MUTE can be controlled. 2000 Jan 10 10
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA Txtal(max) Tstg Tamb Ves PARAMETER digital supply voltage analog supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling note 2 note 3 Notes 1. All supply connections must be made to the same power supply. CONDITIONS note 1 note 1 - - - -65 -40 -3000 -300 MIN.
UDA1320ATS
MAX. 5.0 5.0 150 +125 +85 +3000 +300 V V
UNIT
C C C V V
2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor, except pin 14 which must be specified to -2500V (MIN) and +2500V (MAX). 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. 11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 12 QUALITY SPECIFICATION In accordance with "SNW-FQ-611-E". The number of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192. 13 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 190 UNIT K/W
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
14 DC CHARACTERISTICS
UDA1320ATS
VDDD = VDDA = 3.3 V; Tamb = 25 C; RL = 5 k. All voltages referenced to ground (pins 5 and 15) unless otherwise specified. SYMBOL Supply VDDA VDDD IDDA IDDD VIH VIL ILI Ci VIH VIL DAC Vref Io(max) Rout RL CL Notes 1. All supply connections must be made to the same external power supply unit. 2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 must be used to prevent oscillations in the output operational amplifier. reference voltage maximum output current output resistance load resistance load capacitance note 2 with respect to VSSA (THD + N)/S < 0.1% RL = 5 k 0.45VDDA - - 3 - 0.5VDDA 0.22 0.15 - - 0.55VDDA - 2.0 - 50 V mA k pF DAC analog supply voltage digital supply voltage analog supply current digital supply current note 1 note 1 operation mode operation mode 2.7 2.7 - - 0.8VDDD - - - - -0.5 3.3 3.3 6.5 3.0 - - - - - - 3.6 3.6 - - - 0.2VDDD 1 10 - V V mA mA PARAMETER CONDITIONS MIN TYP. MAX UNIT
Digital input pins HIGH-level input voltage LOW-level input voltage input leakage current input capacitance HIGH-level input voltage LOW-level input voltage V V A pF V
VDDD + 0.5 V
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
15 AC CHARACTERISTICS 15.1 Analog
UDA1320ATS
VDDD = VDDA = 3.3 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k. All voltages referenced to ground (pins 5 and 15) unless otherwise specified. SYMBOL DAC Vo(rms) output voltage (RMS value) unbalance between channels total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio channel separation power supply ripple rejection ratio fripple = 1 kHz; Vripple(p-p) = 100 mV at 0 dB at -60 dB; A-weighted code = 0; A-weighted - - - - - - - 1.0 0.1 -90 -38 100 100 50 - - -85 -35 95 - - V dB dB dB dB dB dB PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Vo
(THD + N)/S S/N cs PSRR
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
15.2 Digital
UDA1320ATS
VDDD = VDDA = 2.7 to 3.6 V; Tamb = -20 to +85 C; RL = 5 k. All voltages referenced to ground (pins 5 and 15); unless otherwise specified. SYMBOL Tsys PARAMETER system clock cycle CONDITIONS fsys = 256fs fsys = 384fs fsys = 512fs tCWL tCWH LOW-level system clock pulse width HIGH-level system clock pulse width fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz Serial input data timing (see Fig.7) Tcy(CLK)(bit) tCLKH(bit) tCLKL(bit) tr tf tsu(i)(D) th(i)(D) tsu(WS) th(WS) Tcy(CLK)(L3) tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tsu(L3)DA th(L3)DA tstp(L3) bit clock period bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time word selection set-up time word selection hold time 300 100 100 - - 20 0 20 10 - - - - - - - - - - - - - - - - - - - - - - 20 20 - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns MIN. 78 52 39 30 40 30 40 TYP. 88 59 44 - - - - MAX. 244 162 122 70 60 70 60 UNIT ns ns ns %Tsys %Tsys %Tsys %Tsys
Microcontroller interface timing (see Figs 4 and 6) L3CLK L3CLK HIGH period L3CLK LOW period L3MODE set-up time L3MODE hold time L3MODE set-up time L3MODE hold time L3DATA set-up time L3DATA hold time L3MODE halt time addressing mode addressing mode data transfer mode data transfer mode data transfer and addressing mode data transfer and addressing mode 500 250 250 190 190 190 190 190 30 190 ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
handbook, full pagewidth
WS th(WS) tf tsu(WS)
tCLKH(bit) tr BCLK tCLKH(bit) Tcy(CLK)(bit) DATAI
tsu(i)(D)
th(i)(D)
MBK075
Fig.7 Serial interface timing.
16 APPLICATION INFORMATION
handbook, full pagewidth
analog supply voltage R2 1
digital supply voltage R3 1
C1 100 F (16 V) C5 100 nF (63 V) VSSA system clock R1 47 BCK WS DATAI APPSEL SYSCLK 15 6
C6 100 nF (63 V) VSSD 5 4 VO(L) C2 47 F (16 V) R5 10 k R4 100 left output
VDDA 13
VDDD
14 1 2 3 7
VO(R)
C3 47 F (16 V) R7 10 k
R6 100
UDA1320A
16 APPL0 APPL1 APPL2 APPL3 11 10 9 8 12
right output
VREF(DAC) C7 100 nF (63 V) C4 47 F (16 V)
MGM818
Fig.8 Application schematic.
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
17 PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
UDA1320ATS
SOT369-1
D
E
A X
c y HE vM A
Z
16
9
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC MO-152 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
18 SOLDERING 18.1 Introduction to soldering surface mount packages
UDA1320ATS
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 18.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
18.5 Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1320ATS
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 Jan 10
18
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
NOTES
UDA1320ATS
2000 Jan 10
19
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/25/02/pp20
Date of release: 2000
Jan 10
Document order number:
9397 750 06675

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